Fully integrated low-noise amplifier

ABSTRACT

A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.

PRIORITY CLAIM

This application claims priority to French Application for Patent No.1650888 filed Feb. 4, 2016, the disclosure of which is incorporated byreference.

TECHNICAL FIELD

The invention relates to low-noise amplifiers, in particular those usedin wireless telecommunications systems and more specifically for mobiletelephony.

BACKGROUND

In a system for transmitting/receiving radiofrequency signals, thereceiving stage comprises an antenna allowing for the reception of asignal that will be transmitted to an amplifier circuit. Elements suchas filters may be inserted between the antenna and the amplifiercircuit. The main purpose of the amplifier is to bring the signal to alevel suitable for the demodulation circuit.

In the case of receivers for wireless telecommunications infrastructure,there is a great need to amplify the received signal with very low noiseand high linearity.

Low-noise amplifiers (LNAs) simultaneously demand a relatively high gaindepending on the standard used, low noise, good input and outputmatching and solid stability with regard to the operating current.

Usually, low-noise amplifiers are equipped with an amplifier circuitgenerally comprising active elements such as transistors, with aninductive degeneration element, with an inductive output element and,additionally, an inductive element for matching the input impedance (orinductive input element). The inductive input element allows, to thefirst order, the imaginary part of the input impedance of the amplifierto be cancelled out, in order to have an input impedance correspondingto the impedance of the system connected to the input (generally 50 ohmsfor an antenna) at the operating frequency of the amplifier. This allowsan optimal transfer of energy.

In order to minimize the noise at frequencies of the order of a GHz, theinductive input element advantageously has a quality factor “Q” that isthe highest possible. An increase in the surface area of the inductiveelement, with respect to a more compact inductive element of the sameinductance, makes it possible to increase the quality factor “Q”. It isfor this reason that usually, for demanding noise specifications, theinductive input element is not integrated on the same, for examplesilicon, substrate as the amplifier circuit, owing to the largepotential size thereof.

The inductive input element is consequently usually positioned on theoutside of the integrated amplifier circuit, for example on a printedcircuit board. These external inductive elements, also called discreteelements, have a high quality factor “Q”.

Currently, in particular within the framework of the Long-Term Evolution(LTE) telecommunications standards, the specifications for a low-noiseamplifier in a frequency band of 2.62 GHz to 2.69 GHz are, for example,a gain of about 13 dB, a noise factor (NF) of about 1 dB, a third-orderinput interception point (IIP3) of about 5 dBm and an isolation S₁₂ ofabout −20 dB.

The isolation parameter S₁₂ represents the way in which a variationapplied to the output of a system is felt at the input thereof, and viceversa. It is then possible to speak of the robustness of theamplification system. The IIP3 parameter is representative of thelinearity of the amplification.

SUMMARY

According to one embodiment, an LNA device is proposed which hasspecifications in accordance with the LTE standards and which iscompletely incorporated into an integrated circuit, having no need of aconnected inductive input-matching element outside the integratedcircuit (also called a discrete element).

The proposed device consequently makes it possible, for example, todecrease the size of the total amplifier circuit, corresponding to thediscrete element and the integrated amplifier circuit in the usual case,and in particular also advantageously makes it possible to easilyincorporate and use the device, for example in a wirelesstelecommunication system.

The proposed amplifier device is obtained by advantageously producing,on one and the same semiconductor substrate equipped with a back end ofline (BEOL) portion, the active amplifier circuit and the inductiveinput element, the amplifier circuit being positioned on the inside ofthe coil of the inductive input element.

Consequently, the proposed device occupies a surface area that issubstantially unchanged with respect to a conventional amplifiercircuit, which additionally requires a discrete element.

Thus, according to one aspect, an integrated amplifier device,advantageously of the low-noise type, is proposed comprising aninductive input element, an amplifier circuit, an inductive outputelement and an inductive degeneration element, the amplifier circuit andsaid inductive output and degeneration elements being located on theinside of said inductive input element.

Thus, the inductive input element is included in the integratedlow-noise amplifier circuit, for example on silicon, for a siliconsurface area that is substantially unchanged with respect to a usualintegrated amplifier circuit which requires an external inductiveelement at the input thereof. The size of the total amplifier system,i.e. including the inductive input element, is consequently notablyreduced while meeting the same specifications.

According to one embodiment, the inductive input element is configuredto permit an input current to flow between an input terminal and theamplifier circuit in a first direction, and the inductive output elementis configured to permit an output current to flow between the amplifiercircuit and a supply terminal in a second direction that is opposite tothe first direction.

This makes it possible to decrease the magnetic coupling between theinductive input element and the inductive output element. Specifically,the magnetic fields generated on the inside of a coil generate amagnetic field that disrupts the surroundings, being able to modulate,through mutual induction, the inductance of neighboring inductiveelements for example.

According to one embodiment, the amplifier circuit comprises at leastone first transistor configured to be in amplification mode and mayadvantageously comprise a cascode assembly comprising the firsttransistor and a second transistor.

Cascode assemblies generally comprise two transistors in series and havethe advantage of ensuring a good isolation parameter S₁₂, with little inthe way of interactions between the output and the input. Furthermore,cascode assemblies generally have a good stability.

According to one embodiment, the inductive input element is coupledbetween the gate of the first transistor and an input terminal of saiddevice, the gate of the first transistor being placed as close aspossible to an end of the inductive input element, i.e., at the smallestdistance permitted by the design rules of the technology in question.

Stated otherwise, the interconnection between the input terminal and thegate of the transistor is optimized so as to obtain the desiredinductance “L” and a quality factor “Q” that is optimal at the workingfrequency. It is the entirety of this interconnection that is optimized,using an electromagnetic simulator, for example.

Such a configuration allows especially the noise performance of thedevice to be optimized by limiting input losses.

According to one embodiment, the inductive degeneration element iscoupled between the source of the first transistor and a groundterminal, the source of the first transistor being placed as close aspossible to one end of said inductive degeneration element and theground terminal being placed as close as possible to another end of saidinductive degeneration element, i.e., at the smallest distancespermitted by the design rules of the technology in question.

Stated otherwise, the interconnection between the source of the firsttransistor and the ground terminal is optimized so as to obtain thedesired inductance “L” and a quality factor “Q” that is optimal at theworking frequency. It is the entirety of this interconnection that isalso optimized, using an electromagnetic simulator for example.

In order to be subjected to a minimum of parasitic signals, saidinductive input element may advantageously comprise a metal track in theform of a non-intersecting spiral. Indeed, intersecting metal tracksintroduce restrictive parasitic components.

An integrated circuit is also proposed incorporating an amplifier devicesuch as defined above.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent uponexamining the detailed description of completely non-limitingembodiments, and the appended drawings in which:

FIG. 1 shows an exemplary receiving stage of a telecommunication system;

FIG. 2 shows an exemplary circuit diagram of an amplifier device; and

FIG. 3 shows an exemplary architecture of an amplifier device structure.

DETAILED DESCRIPTION

FIG. 1 shows an exemplary conventional receiving stage, for example of atelecommunication system, comprising an antenna 1, directly coupled to alow-noise amplifier (LNA) 2.

The amplified signal output from the LNA is mixed by two mixers 3 with alocal oscillator signal 4 and this local oscillator signal phase-shiftedby 90° by a phase shifter 5, respectively.

At the output of the mixers 3, analog signals transposed onto thechannel I and onto the channel in phase quadrature Q are obtained, whichwill subsequently be filtered by filters 6 and converted into digitalsignals by an analog-digital converter (CAN) 7, then processed, inparticular demodulated, by a processing stage (MPU) 8.

FIG. 2 shows a circuit diagram of an, advantageously low noise,amplifier device, comprising an amplifier circuit CA and an inductiveinput element Lin, an inductive degeneration element Ldeg and aninductive output element Lout.

The amplifier circuit CA comprises active elements, such as transistorsfor example.

The amplifier device 2 conventionally comprises supply Vdd and groundGND terminals, an input terminal receiving signal RF_IN+VG_GO1, anoutput terminal generating signal RF_OUT, and a bias voltage terminalreceiving bias voltage VG_GO2.

The amplifier circuit CA here comprises a cascode assembly of twotransistors M1, M2 in series, the source of the transistor M2 beingconnected to the drain of the transistor M1, used in amplification mode.The amplification function could be ensured by a common-source assembly,for example, or any other assembly ensuring this function.

The source of the transistor M1 is connected to ground via the inductivedegeneration element Ldeg.

The inductive input element Lin is connected between the input receivingsignal RF_IN+VG_GO1 and the gate of the transistor M1.

The gate of the transistor M2 is connected to a node linking a biasresistor Rbias connected to the bias voltage terminal receiving biasvoltage VG_GO2 and a decoupling capacitor Cgo2 connected to the groundGND.

The drain of the transistor M2 is connected to an output node linkingthe output generating the signal RF_OUT of the amplifier 2 via an outputcapacitor Cout and an inductive output element Lout connected to thesupply terminal Vdd. The supply terminal Vdd is directly connected to adecoupling capacitor Cvdd linked to ground GND.

Thus, the transistor M1 is controlled via the gate thereof by the inputsignal RF_IN+VG_GO1, said input signal comprising the signal to beamplified RF_IN transmitted by an antenna for example, and a biasvoltage VG_GO1 biasing the transistor M1 to a given on-statecorresponding to a desired power consumption.

The input signal RF_IN+VG_GO1 resistively generates an input currentIRFin that flows through the inductive input element Lin.

The inductive degeneration element Ldeg allows the input impedancematching to be optimized in combination with the inductive input elementLin in particular. More specifically, to the first order, the inductiveinput element Lin allows the imaginary part of the input impedance ofthe LNA to be cancelled out and the inductive degeneration element Ldegallows the real part of the input impedance to be set to 50 ohms, for areference impedance of 50 ohms.

The resistance Rbias allows the gate of the transistor M2 to be biasedwhile presenting a high impedance to the input radiofrequency signal.The capacitor Cgo2 allows the radiofrequency signal entering at thedrain of the transistor M2 to see ground.

The transistor M2 is controlled by the bias voltage VG_GO2, which maybe, for example, of 1.5 V so as to bias the drain of the transistor M1to 1.2 V, in the case of a supply voltage Vdd at 2.5 V.

An output current IRFout, corresponding to the amplified input currentIRFin, flows into the inductive output element Lout and into the outputcapacitor Cout.

The transistor M1 has been shown in body contact configuration, i.e. thesource terminal and the substrate (“body”) terminal of the transistor M1are linked, ensuring good linearity of amplification. The transistor M2has been shown in floating body configuration, i.e. the potential of thesubstrate (“body”) thereof is floating, facilitating the architecturewhile having a satisfactory output impedance.

Preferably, the transistors M1 and M2 are produced on and in asemiconductor substrate of a silicon-on-insulator (SOI) technology. SOItechnology allows higher quality factors to be obtained in comparisonwith other technologies.

However, the transistors M1 and M2 may, depending on the need, be in aconfiguration other than the body contact and floating bodyconfiguration respectively, or be of another nature, for example bipolaror CMOS transistors, or produced in BiCMOS (bipolar and CMOS) technologysupported on and in a semiconductor substrate.

The decoupling capacitor Cvdd allows potential variations on the supplyVdd to be removed and filtered to ground.

The inductive output element Lout in particular allows the outputimpedance to be matched to a required value. The assembly of theinductive output element Lout and of the output capacitor Cout allowsthe output matching desired at the working frequency to be obtained.

FIG. 3 shows an architecture of an, advantageously low noise, integratedamplifier device structure 2 corresponding to the circuit describedabove in relation to FIG. 2, in which the amplifier circuit CA and theinductive degeneration Ldeg and output Lout elements are positioned onthe inside of the inductive input element Lin.

The integrated amplifier device 2 is produced, according to thisarchitecture, on a single semiconductor substrate surmounted by a backend of line (BEOL) portion and conventionally comprises pads forconnecting to the supply Vdd, ground GND, input RF_IN+VG_GOL outputRF_OUT and bias voltage VG_GO2 terminals.

The various pads for connecting to the ground terminals GND shown inFIG. 3 are all linked to a ground plane that is not shown in thisrepresentation, corresponding to a uniform common ground.

Usually, the amplifier circuit CA is produced in and on thesemiconductor substrate and the inductive elements in the metallizationlevels of the back end of line portion.

These connection pads are intended, for example, to receivemetallization bumps in order to enable flip chip interconnection. Theseconnection pads may also, for example, allow probes to be applied inorder to characterize the circuit in terms of small signal performance,noise and linearity.

The inductive input element Lin is here formed by a metal track in theform of a non-intersecting flat spiral, i.e. the metal track windsaround without unwinding, one end of the inductive input elementconsequently being located on the outside of the spiral and the otherend on the inside of the spiral.

Consequently, in this configuration that advantageously avoids thesuperposition of metal tracks of the inductive input element Lin, thisbeing a source of parasitic components, the pad for connecting to theinput terminal to receive the signal RF_IN+VG_GO2 is located on theoutside of the spiral.

The pad for connecting to the bias voltage terminal for receiving thebias voltage VG_GO2 is, in this non-limiting representation, alsolocated on the outside of the inductive input element Lin, but accordingto the general features, nothing prevents an embodiment comprising thispad located on the inside of the inductive input element Lin.

The transistor M1 is positioned very close to the inner end of theinductive input element Lin in order to minimize the length of aconnecting track Pg linking said inductive input element Lin to the gateof the transistor M1. In particular, this allows losses at the input ofthe amplifier circuit CA to be reduced.

The inductive degeneration element Ldeg is configured so as to be ascompact as possible. Connecting tracks Ps and Pgnd at the ends of theinductive element Ldeg and the inductive element Ldeg are optimizedtogether, so as to obtain the desired inductance “L” and a qualityfactor “Q” that is optimal at the working frequency.

In particular, this allows the surface area occupied on the inside ofthe inductive input element Lin to be decreased.

In this representation, in contrast to the inductive input element Lin,the inductive degeneration element Ldeg is formed by a flat spiral thatintersects itself, i.e. in the form of a metal track that winds andunwinds, and the two ends of which are on the outside of the spiral.

The decoupling capacitors Cgo2 and Cvdd of FIG. 2 are shown here in anon-limiting manner in the respective combinations of capacitor pairsCgo2_1 and Cgo2_2, Cvdd_1 and Cvdd_2. Each pair of capacitors comprisesa capacitor (Cgo2_1, Cvdd_1) produced, for example, in MOM(metal-oxide-metal) technology comprising intersecting metal “fingers”separated by oxide spaces, and a capacitor (Cgo2_2, Cvdd_2) produced,for example, in PIPCAP (poly-insulator-poly capacitor) technology bysuperposing layers of polysilicon, insulator and polysilicon.

These two capacitor technologies are well known to those skilled in theart and are used in combination in order to benefit from the advantagesof each thereof. These advantages are based on linearity and densitycriteria, i.e. capacitance per μm².

The inductive output element Lout is positioned in a configuration suchthat, during normal operation of the amplifier device 2, the outputcurrent portion IRFout flowing through the inductive output element Loutflows in a direction of rotation that is opposite to the direction ofrotation of the input current IRFin flowing through the inductive inputelement Lin.

Specifically, in the configuration shown in FIG. 3, the input currentIRFin flows through the inductive input element Lin in an anticlockwisedirection, from the input terminal RF_IN+VG_GO1 to the gate of thetransistor M1. In this same configuration, the output current portionIRFout flows through the inductive output element Lout in a clockwisedirection, from the drain of the transistor M2 to the supply terminalVdd.

The magnetic fields generated by the two inductive input Lin and outputLout elements are consequently in opposite directions and the couplingof one to the other is very much reduced.

This configuration allows an improved isolation factor S₁₂ to beobtained, for example a reduction of substantially 6 dB with respect toa configuration in which the current flows in the same direction in saidtwo inductive elements.

The other components of the amplifier circuit CA, described above inrelation to FIG. 2, are advantageously positioned on the surface areaavailable on the inside of the inductive input element Lin and theconfiguration shown in FIG. 3 is, geometrically speaking, in no waylimiting.

1. An integrated amplifier device, comprising: an inductive inputelement, an amplifier circuit, an inductive output element, and aninductive degeneration element, wherein the amplifier circuit, saidinductive output element and said inductive degeneration element arelocated on an inside of said inductive input element.
 2. The deviceaccording to claim 1, wherein the inductive input element is configuredto permit an input current to flow between an input terminal and theamplifier circuit in a first direction, and the inductive output elementis configured to permit an output current to flow between the amplifiercircuit and a supply terminal in a second direction that is opposite tothe first direction.
 3. The device according to claim 1, wherein theamplifier circuit comprises at least one first transistor configured tooperate in an amplification mode.
 4. The device according to claim 3,wherein the amplifier circuit comprises a cascode assembly comprisingthe at least one first transistor and a second transistor.
 5. The deviceaccording to claim 3, wherein the inductive input element is coupledbetween a gate of the at least one first transistor and an inputterminal of said device, the gate of the at least one first transistorbeing placed adjacent an end of the inductive input element.
 6. Thedevice according to claim 3, wherein said inductive degeneration elementis coupled between a source of the at least one first transistor and aground terminal, the source of the at least one first transistor beingplaced adjacent to one end of said inductive degeneration element andthe ground terminal being placed adjacent another end of said inductivedegeneration element.
 7. The device according to claim 1, wherein saidinductive input element comprises a metal track in the form of anon-intersecting spiral, with the amplifier circuit, said inductiveoutput element and said inductive degeneration element located inside ofsaid non-intersecting spiral.
 8. The device according to claim 1,wherein the amplifier circuit, said inductive output element and saidinductive degeneration element are supported by an integrated circuitsubstrate.
 9. An integrated amplifier device, comprising: asemiconductor substrate; a back end of line structure supported by saidsemiconductor substrate; an amplifier circuit formed in and on saidsemiconductor substrate; an inductive input element, inductive outputelement and inductive degeneration element provided within said back endof line structure; wherein said inductive input element comprises aspiral shape; and wherein the amplifier circuit, inductive outputelement and inductive degeneration element are located within the spiralshape of the inductive input element.
 10. The device of claim 9, whereinsaid back end of line structure includes metallization levels and theinductive input element, inductive output element and inductivedegeneration element are formed in one or more of the metallizationlevels.
 11. The device of claim 9, wherein inductive output element alsohas a spiral shape, and where current flowing in the spiral shape of theinductive input element flows in an opposite direction of flowing in thespiral shape of the inductive output element.
 12. The device of claim11, wherein the spiral shape of said inductive input element is in theform of a non-intersecting spiral and wherein the spiral shape of saidinductive output element is in the form of an intersecting spiral.